1. Field of the Invention
The present invention relates in general to a structure and operating method for a nonvolatile memory cell. In particular, the present invention relates to a nonvolatile memory cell capable of operating at low voltage and its operating method.
2. Description of the Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, in a myriad of applications. A nonvolatile memory is capable of changing its on/off state at the same gate voltage with presence/absence of charge carriers in the charge carrier storage structure. The charge carrier storage structure can be formed by a floating gate electrode or a silicon nitride film. A dielectric carrier trap structure having a silicon nitride film sandwiched between silicon oxide films is known as an oxide-nitride-oxide (ONO) film, and the nonvolatile memory having the dielectric carrier trap structure is called nitride read only memory (NROM).
A traditional NROM is shown in FIG. 1. In programming, electrons flowing from the substrate 12 are trapped in the memory position Ma or/and Mb in the silicon nitride layer 20 near the n-doped region 14 and 16. The silicon nitride layer 20 is sandwiched between the top oxide layer 22 and the bottom oxide layer 18. In writing data in the silicon nitride layer 20 near the n-doped region 16, that is, the right side, a ground voltage is applied to the n-doped region 14, a positive voltage, e.g., 6 V is applied to the n-doped region 16, and a high voltage, e.g., 8 V is applied to the control gate 24, as shown in Table 1. In this manner, the n-doped regions 14 and 16 function as source and drain respectively. These electrons are accelerated in the depletion layer and become hot electrons which pass through the bottom oxide film 18 and are injected into the silicon nitride film 20 at a memory position Mb. This writing mode is called channel hot electron (CHE) injection.
In erasing data, as shown in Table 1, a positive voltage, e.g., 7 V is applied to the n-doped region 16, and a negative voltage, e.g., −12 V is applied to the control gate 24. In this manner, the holes generated by band-to-band tunneling (BTB tunneling) pass through the bottom oxide layer 18 and are injected into the silicon nitride layer 20 to neutralize the stored charges at the memory position Mb near the n-doped region 16. This erasing mode is called band-to-band tunneling.
TABLE 1programmingerase(memory(memoryposition Mb)position Mb)Voltage applied to the n-doped region 14Ground(source)Voltage applied to the n-doped region 166 V   7 V(drain)Voltage applied to the control gate 248 V−12 V
However, when executing programming and erase, a higher voltage is needed. Thus, high voltage elements are needed in circuit design and complexity of process is increased.
Furthermore, hot electrons and hot holes are generated in programming and erasure. Thus, the reliability of the bottom oxide layer is reduced.
Moreover, when electrons are stored at a position Mbb different from a target memory position Mb, as shown in FIG. 2, the electrons at the changed memory position Mbb cannot be erased by a usual erase operation. For the opposite situation, when holes are injected at a position Mbb different from the predetermined memory position Mb, the electrons at the target memory position Mb cannot be neutralized by the erase operation. No matter which situation occurs, overprogramming will be encountered in the next programming operation. Because the injection positions of electrons and holes are different, after long use, electrons and holes not only cannot be neutralized but will also encounter lateral diffusion.